The present invention relates generally to integrated circuits and, more particularly, to a comparator circuit having hysteresis.
A comparator is a circuit that compares the voltage levels of two input signals and generates an output signal that indicates whether one of the input signals is greater than the other input signal. For example, in some applications, the second input signal is a fixed reference signal, and the comparator generates (i) a high voltage output signal (e.g., corresponding to a logical one value) when the first input signal is greater than the second, reference input signal and (ii) a low voltage output signal (e.g., corresponding to a logical zero value) when the first input signal is not greater than the second, reference input signal.
In some noisy applications, the first input signal and possibly even the second, reference input signal have relatively high frequency voltage fluctuations that can result in chattering where the output signal toggles rapidly between the high and low voltage output levels when the two input signals have similar voltage levels.
To avoid chattering, it is known to design a comparator with built-in hysteresis, where the threshold voltage level required for the output signal to transition from low to high is higher than the threshold voltage level required for the output signal to transition from high to low. For example, in one implementation of hysteresis, if the first input signal was previously substantially less than the second input signal such that the output signal was previously low, then the comparator output will transition from low to high only when the voltage of the first input signal is greater than the voltage of the second input signal by at least a specified first hysteresis voltage difference. Furthermore, if the first input signal was previously substantially greater than the second input signal such that the output signal was previously high, then the comparator output will transition from high to low only when the voltage of the first input signal is less than the voltage of the second input signal by at least a specified second hysteresis voltage difference. In this particular situation, the total hysteresis voltage difference of the comparator is the sum of the first and second hysteresis voltage differences. Note that, in other implementations, only one of the two hysteresis voltage differences is needed to provide hysteresis.
FIG. 1 is a schematic circuit diagram of a conventional comparator 100 having built-in hysteresis. The comparator 100 has an input stage 110, hysteresis current-injection circuitry 120, an output stage 150, a Schmitt trigger circuit 160, and two inverters 170 and 180. The input stage 110 comprises p-type transistors P0-P1, n-type transistors N0-N1, and two constant-current sources I1 and I2. The hysteresis current-injection circuitry 120 includes p-type transistors P2 and P3 and a constant-hysteresis-current source Ihy. The output stage 150 comprises p-type transistors P4-P7 and n-type transistors N4-N7. In one implementation, the p-type transistors in the comparator 100 are all PMOS transistors, and the n-type transistors are all NMOS transistors.
The comparator 100 is a differential comparator that converts a voltage difference INP, INN applied to the differential input pairs P0/P1 and N0/N1 of the input stage 110 into a differential current that is injected into the output stage 150, which causes the Schmitt trigger circuit 160 to fire when the rising current level in one leg of the output stage 150 crosses the falling current level in the other leg of the output stage 150.
The output stage 150 includes a P cascade comprising (i) an upper P gate formed by the transistors P4 and P5 and (ii) an intermediate P gate formed by the transistors P6 and P7. The output stage 150 also includes an N cascade comprising (i) an intermediate N gate formed by the transistors N6 and N7 and (ii) a lower N gate formed by the transistors N4 and N5. The reference signal VPU is the voltage bias for the upper P gate, the reference signal VPM is the voltage bias for the intermediate P gate, and the reference signal VNM is the voltage bias for the medium N gate. Note that bias voltage for the lower N gate of the N cascade is the drain voltage of the transistors P6 and N6.
The comparator 100 is designed such that, for normal operations, the current IP4 through the transistor P4 is equal to the current IP5 through the transistor P5, which current is also referred to herein as the bias current IBIAS. In addition, the current I1 generated by the current source I1 is equal to the current I2 generated by the current source 12, which current is also referred to herein as the tail current ITAIL.
In general, the current IN4 flowing through the transistor N4 is given by Equation (1) as follows:IN4=IP4+IP2−IN0+IP0  (1)and the current IN5 flowing through the transistor N5 is given by Equation (2) as follows:IN5=IP5+IP3−IN1+IP1.  (2)
Assume that initially the input signal INP is low (i.e., at or near the ground voltage GND), the complementary input signal INN is high (i.e., at or near the supply voltage VDD), the output signal OUT is low, and the complementary output signal OUTN is high. In that case, the transistor P2 will be on, the transistor P3 will be off, and the hysteresis current Ihy will inject into the drain of the transistor N0. In that case, the current IN4 through the transistor N4 will be given by Equation (3) as follows:IN4=IP4+IP2−IN0+IP0=IBIAS+Ihy−IN0+IP0  (3)and the current IN5 through the transistor N5 will be given by Equation (4) as follows:IN5=IP5+IP3−IN1+IP1=IBIAS−IN1+IP1.  (4)Thus, when the input signal INP is low and the complementary input signal INN is high, IN1>IN0, IP0>IP1, and the current IN4 through the transistor N4 is greater than the current IN5 through the transistor N5.
As the input signal INP increases and the complementary input signal INN decreases, the current through the transistor N0 increases, and the current through the transistor N1 decreases. At the same time, the current through the transistor P0 decreases, and the current through the transistor P1 increases. As such, the current IN4 through the transistor N4 decreases and the current IN5 through the transistor N5 increases.
If and when the falling current IN4 through the transistor N4 becomes equal to the rising current IN5 through the transistor N5, the output of the Schmitt trigger circuit 160 will switch from low to high, which causes (i) the output signal OUT to go from low to high and (ii) the complementary output signal OUTN to go from high to low, thereby turning off the transistor P2, turning on the transistor P3, and switching the hysteresis current Ihy from output leg of the transistor N4 to the output leg of the transistor N5 all at once. The Schmitt trigger circuit 160 is a conventional digital buffer circuit with its own hysteresis voltage, whose function is to depress the influence of noise at the output of the comparator 100.
If the input signal INP continues to increase and the complementary input signal INN continues to decrease, the current IN5 through the transistor N5 will become greater than the current IN4 through the transistor N4. With the output signal OUT high and the complementary output signal OUTN low, the transistor P2 will be off, the transistor P3 will be on, and the hysteresis current Ihy will inject into the drain of the transistor N1. In that case, the current IN4 through the transistor N4 will be given by Equation (5) as follows:IN4=IP4+IP2−IN0+IP0=IBIAS+0−ITAIL+0=IBIAS−IN0+IP0  (5)and the current IN5 through the transistor N5 will be given by Equation (6) as follows:IN5=IP5+IP3−IN1+IP1=IBIAS+Ihy−0+ITAIL=IBIAS+Ihy+−IN1+IP1.  (6)Thus, when the input signal INP is high and the complementary input signal INN is low, IN0>IN1, IP1>IP0, and the current IN5 through the transistor N5 is greater than the current IN4 through the transistor N4.
If and when the input signal INP decreases and the complementary input signal INN increases, the current through the transistor N0 decreases, and the current through the transistor N1 increases. At the same time, the current through the transistor P0 increases, and the current through the transistor P1 decreases. As such, the current IN4 through the transistor N4 increases and the current IN5 through the transistor N5 decreases.
If and when the rising current IN4 through the transistor N4 becomes equal to the falling current IN5 through the transistor N5, the output of the Schmitt trigger circuit 160 will switch from high to low, which causes (i) the output signal OUT to go from high to low and (ii) the complementary output signal OUTN to go from low to high, thereby turning on the transistor P2, turning off the transistor P3, and switching the hysteresis current Ihy from output leg of the transistor N5 back to the output leg of the transistor N4 all at once.
The Schmitt trigger circuit 160 ensures that either (i) OUT=0 and OUTN=1 or (ii) OUT=1 and OUTN=0. As such, either (i) IP2=Ihy and IP3=0 or (ii) IP2=0 and IP3=Ihy. In general, when the current IN4 through the transistor N4 is equal to the current IN5 through the transistor N5, Equations (1) and (2) yield Equation (7) as follows:IP4+IP2−IN0+IP0=IP5+IP3−IN1+IP1.  (7)Since IP4=IP5, Equation (7) can be rewritten as Equation (8) as follows:|(IP1−IP0)+(IN0−IN1)|=Ihy  (8)where the sign depends on which of the two output conditions exist.
The inclusion of the hysteresis current-generation circuitry 120 in the comparator 100 results in the voltage level of the rising input signal INP at which the output signal OUT switches from low to high being higher than the voltage level of the falling input signal INP at which the output signal OUT switches from high to low. This hysteresis voltage difference )V inhibits unwanted chattering in the output signal OUT in noisy environments.
The relationships between the hysteresis voltage difference )V and the differential currents flowing through the two pairs of input transistors P0, P1 and N0, N1 can be expressed by Equations (9) and (10) as follows:gmp*ΔV=IP1−IP0  (9)andgmn*ΔV=IN0−IN1,  (10)where gmp is the transconductance of the input pair P0, P1, and gmn is the transconductance of the input pair N0, N1. The total transconductance gm of the comparator 100 is the sum of the transconductances of the two input pairs or (gmp+gmn). Substituting Equations (9) and (10) for gmp and gmn and applying Equation (8) yields Equation (11) as follows:ΔV=Ihy/gm.  (11)Equation (11) implies that, for a constant-hysteresis-current source Ihy, the hysteresis voltage difference )V will be constant for all operating conditions if the total transconductance gm of the comparator 100 is also constant.
However, the transconductance gm of the comparator 100 is not constant for all common-mode voltage levels Vcm, but is instead given by Equation (12) as follows:
                                                                        I                D                                                              ζ                  n                                *                                  V                  T                                                                                                        V                ⁢                cm                            <                              V                thn                                                                                        gm              =                                                                    I                    D                                                        V                    T                                                  ⁢                                  (                                                            1                                              ζ                        n                                                              +                                          1                                              ζ                        p                                                                              )                                                                                                        V                thn                            ≤                              V                ⁢                cm                            ≤                                                V                  DD                                -                                  V                  thp                                                                                                                        I                D                                                              ζ                  p                                *                                  V                  T                                                                                                        V                ⁢                cm                            ≥                                                V                  DD                                -                                  V                  thp                                                                                        (        12        )            where:                ID is the current flowing through the drain terminal of an n-type or p-type input MOS transistor (e.g., N0, N1, P0, P1) operating in the weak inversion region. In this case, ID=0.5*ITAIL;        VT is the thermal voltage;        ζn is a factor which stems from a voltage divider between the oxide capacitance Cox and the depletion capacitance Cjsn in an n-type input MOS transistor (e.g., N0, N1), where        
            ζ      n        =                  Cjsn        +        Cox            Cox        ;                ζp is a factor which stems from a voltage divider between the oxide capacitance Cox and the depletion capacitance Cjsn in a p-type input MOS transistor (e.g., P0, P1), where        
            ζ      p        =                  Cjsp        +        Cox            Cox        ;                Vcm is the common-mode voltage, which is equal to (INP+INN)/2;        Vthn is the threshold voltage for the n-type transistor;        Vthp is the threshold voltage for the p-type transistor.        
When the currents I1 and I2 are equal, then the hysteresis voltage difference ΔV is given by Equation (13) as follows:
                    ΔV        =                              kV            T                    /                      (                                          1                                  ζ                  n                                            +                              1                                  ζ                  p                                                      )                                              (        13        )            where k is the ratio Ihy/ID.
As shown in Equation (X1), the transconductance gm of the comparator 100 is different for different ranges of the common-mode voltage Vcm. As such, Equation (11) implies that the hysteresis voltage difference ΔV is not constant for all values of the common-mode voltage level Vcm. In particular, when the input pair N0, N1 is operated at sub-threshold (i.e., in the weak inversion region of the devices), the comparator 100 suffers transconductance degeneration in which the hysteresis curve increases sharply when the common-mode voltage approaches either the supply voltage VDD or the ground voltage GND. Such non-uniform hysteresis behavior with varying common-mode voltage level is undesirable in certain applications.